timing-constraints

Expert skill for developing and validating timing constraints. Writes SDC (Synopsys Design Constraints) and XDC files for FPGA timing closure.

Also installable via skills CLI

npx skills add a5c-ai/babysitter/plugins/babysitter/skills/babysit/process/specializations/fpga-programming/skills/timing-constraints

Source

Path:plugins/babysitter/skills/babysit/process/specializations/fpga-programming/skills/timing-constraints/SKILL.md(main)

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