verilog-sv-language

Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.

by a5c-ai· Repository·other
Run in AgentAreaBrowse All Skills
Also installable via skills CLI
npx skills add a5c-ai/babysitter/plugins/babysitter/skills/babysit/process/specializations/fpga-programming/skills/verilog-sv-language

Source

Repo:github.com/a5c-ai/babysitter
Path:plugins/babysitter/skills/babysit/process/specializations/fpga-programming/skills/verilog-sv-language/SKILL.md(main)

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