assertion-design

SystemVerilog Assertions (SVA) as executable specifications. Use when defining timing requirements, protocol specifications, or formal properties for RTL verification.

by MameMame777· Repository·other

Run in AgentArea Browse All Skills

Also installable via skills CLI

npx skills add MameMame777/AXIUART_RV32I/.github/skills/assertion-design

Source

Repo:github.com/MameMame777/AXIUART_RV32I

Path:.github/skills/assertion-design/SKILL.md(main)

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