SystemVerilog Assertions (SVA) as executable specifications. Use when defining timing requirements, protocol specifications, or formal properties for RTL verification.
.github/skills/assertion-design/SKILL.md
Use this skill when the user asks to save, remember, recall, or organize memories. Triggers on: 'remember this', 'save t...
CLI tool for configuring and monitoring Claude Code
指导Claude按照二哥的风格撰写求职类文章，包括公司薪资爆料、年终奖盘点、求职攻略、offer选择建议等内容。