UVM testbench architecture and verification methodology for SystemVerilog. Use when creating UVM tests, agents, drivers, monitors, sequences, or scoreboards.
.github/skills/uvm-verification/SKILL.md
Use this skill when the user asks to save, remember, recall, or organize memories. Triggers on: 'remember this', 'save t...
CLI tool for configuring and monitoring Claude Code
指导Claude按照二哥的风格撰写求职类文章，包括公司薪资爆料、年终奖盘点、求职攻略、offer选择建议等内容。