uvm-verification

UVM testbench architecture and verification methodology for SystemVerilog. Use when creating UVM tests, agents, drivers, monitors, sequences, or scoreboards.

by MameMame777· Repository·other
Run in AgentAreaBrowse All Skills
Also installable via skills CLI
npx skills add MameMame777/AXIUART_RV32I/.github/skills/uvm-verification

Source

Repo:github.com/MameMame777/AXIUART_RV32I
Path:.github/skills/uvm-verification/SKILL.md(main)

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uvm-verification | AgentArea Skills