Debug SystemVerilog testbench failures in the SVC project. Use when a testbench fails (make <module>_tb), to analyze CHECK_* assertion failures, watchdog timeouts, or unexpected signal values. Provide
docs/skills/debug-tb
Use when you have lint errors, formatting issues, or before committing code to ensure it passes CI.
This skill should be used when the user asks to "update documentation for my changes", "check docs for this PR", "what d...
Write docstrings for PyTorch functions and methods following PyTorch conventions. Use when writing or updating docstring...